- Our senior consultant has 25 years of industry experience in both RF/wireless product development and mixed-signal IC design, with a strong track record of bringing innovative designs to high volume production.
- 49 issued U.S. Patents with major U.S. corporations in the areas of Fractional-N PLLs, calibration algorithms and low power design.
- Frequency Generation circuit and system design (PLL, VCO, etc.)
- Fully integrated Fractional-N and Integer-N PLL frequency synthesizers
- RF VCOs, Crystal oscillators, ring oscillators
- Low noise input/output buffers and drivers
- High speed prescaler and divider circuits, including robust dynamic logic techniques and detailed timing analysis for custom high speed circuits.
- Calibration and Control Systems (mixed analog/digital)
- Auto-correction methods for PVT variation or to optimize over wide ranges of operation.
- RF/Analog IP Integration
- Analog IP selection and integration
- floorplanning and isolation strategies
- pad ring, power supply and bias planning and design
- Behavioral Modeling and Design Verification
- Matlab, Octave, C, Verilog, Verilog-A, Verilog-AMS model development
- Mixed-signal and full chip simulation
- Analog and mixed-signal verification and regression testing
- Production test planning
- General/Other
- Experience with 1um down to 45nm CMOS, BiCMOS and CMOS SOI circuit design.
- ESD I/O Pad Library development for RF/Analog/Mixed-Signal ICs
- Robust power-on reset (POR) design and start-up sequencing
- Digital design for serial interfaces (I2C, SPI, MIPI RFFE and custom interfaces)
- E-Fuse integration with digital interfaces and automatic sensing systems
- System and digital design of calibration/control systems for PLLs and transmit and receive paths
- Analog and mixed-signal design (filters, data converters) for calibration/control systems
- RF design and system engineering for both receive and transmit paths
- Debug and improvement of existing circuits and systems
- Circuit and chip level layout and parasitic extraction
- Full chip database integration and verification
- Revision control methodologies
- Project planning and design team organization
- Detailed design reviews, specification development, prior art discussions
- Cadence Design Systems (Virtuoso platform for schematics and layout including LayoutXL, Spectre RF simulator, both IC 5.1 and IC 6.1)
- Various LVS/DRC/PEX tools, e.g. Dracula, Diva, Calibre, Assura
- Verilog synthesizable RTL and test bench development
- System Verilog RTL and test bench development, incl. object oriented methods
- Verilog-A and Verilog-AMS behavioral model development
- Nanosim and UltraSim full chip transistor-level simulation
- Cadence AMS Designer / irun mixed mode simulation
- Synopsys DC, Cadence RTL Compiler, First Encounter, and Mentor FastScan for synthesis, place & route and ATPG (scan test generation) for small to medium sized digital blocks
- Scripting and programming with Matlab, Perl, Python, C, Skill and Ocean
- Cadence tool and PDK installation
- Cliosoft SOS installation
- 49 issued patents, numerous publications
- details available on request