InPhase Design - Examples

Examples of recent consulting work

Developed the system architecture, communication protocol and digital system design for a very low power, energy constrained device.
The digital system design employs novel hierarchical clock gating techniques.
The protocol is a flexible, crystal-less protocol suitable for low data rate intermittent communications with minimal power consumption at the receiver.
Prepared link budget analyses, battery life analyses and surveyed existing solutions.
Prepared disclosures and assisted with writing of patent applications with the customer's attorneys.

Analyzed the PLL to identify circuit and system issues contributing to degraded performance.
Provided test benches for charge pump linearity and delay variation simulations.
Provided Matlab/Octave post-processing scripts for analyzing full chip transistor and mixed transistor/behavioral simulations to identify sources of pattern dependent jitter.
Co-developed circuit design improvements with the customer's design team.

Matlab-based phase noise analysis program using calculated noise and transfer function data, or accepting data from simulation results.

Multiple operating modes and multiple specification masks for each mode are supported.
The code is factored into common functions and is cleanly split between reusable modules for other other projects, and modules unique to the present product.

Full chip verification for a large RF/mixed-signal transceiver IC and for a multiband front-end IC.

Developed batch-mode simulation scripts and regression test methods for Verilog-AMS simulations.

Developed and/or improved baseband and frequency shifted models of the RF path for improved simulation speed
Implemented and documented design flows for mixed-signal AMS simulations using the Cadence oss/irun flow for the development team.
Implemented and documented full chip transistor level simulations using UltraSim and AMS/Ultrasim.

Custom, mixed-voltage serial interface including ESD I/O pads, power-on resets, custom high voltage registers, synthesized low-voltage controller core (Verilog RTL, Cadence RC and Encounter).

Worked with the customer's system engineers to clarify and complete the design specifications
Provided complete design and design flow documentation and training.
Engaged engineers at the foundry and at the CAD vendor to identify best approaches and for detailed technical reviews.

Developed and validated EM analysis and design equations for air coupled transformers and various coil configurations.
Prototyped and demonstrated proof of concept circuits and coils.

Examples of completed major designs and projects (prior experience)

Example circuits (prior experience)

Innovative fractional-N offset-loop PLL architectures to minimize spur and blocking problems
Spur free fractional-N modulator architectures
Fast, automatic PLL gain and transfer function calibration algorithms and mixed-signal circuits
Low noise, high linearity charge pump phase-frequency detectors
Low power all-CMOS RF prescalers and programmable dividers
Fully differential crystal oscillators
Low noise, low harmonic buffers and drivers
Complete RF/Analog/Digital ESD I/O pad libraries
Digital controllers, calibration systems and interface circuits
Integrated SiGe upconverter/driver IC
Complete paging receiver design (discrete, board level)

Example simulation and verification techniques (prior experience)

Fast behavioral models in Verilog-AMS for complete RF Frac-N PLL and Transmitter
Verilog simulation test bench platform for full chip transciever simulations
Fast event-driven PLL simulator in C, including circuit non-idealities and noise
Matlab simulation scripts for complete phase noise analysis of Frac-N PLLs
Matlab simulation scripts and development of custom DSP based tests for fast, end-to-end Rx and Tx production test

Key words: PLL design consultant, PLL expert, mixed-signal design consultant, IC integration consultant, full chip verification